A Low-Power BiCMOS 4-Element Phased Array Receiver for 76–84 GHz Radars and Communication Systems

Abstract

This paper presents a 76-84 GHz low-power 4- element phased array receiver built using a 0.13 μm BiCMOS process. The power consumption is reduced by using a single-ended design and alternating the amplifiers and phase shifter cells to result in a low noise figure at a low power consumption. A variable gain amplifier and an 11 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> trim bit are used to correct for the rms gain and phase errors at different operating frequencies. The phased array consumes 32 mW per channel and results in a gain of 10-19 dB at 76-84 GHz, a noise figure of 10.5 ±0.5 dB at 80 GHz and an rms gain and phase error <;0.8 dB and <;7.2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> , respectively, up to 81 GHz, and <;1.1 dB and 10.4 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> up to 84 GHz. The phased array also shows a channel to channel coupling of <; - 30 dB up to 84 GHz. To our knowledge, this work presents state-of-the-art on-chip performance at W-band frequencies.