A low-power and small-area all-digital delay-locked loop with closed-loop duty-cycle correction

Abstract

In this paper, we propose a delay-locked loop (DLL) with a closed-loop duty-cycle correction (DCC) circuit. The proposed DCC circuit does not require additional blocks for DCC, and this enables it to have a significantly reduced power consumption and area. To increase DCC accuracy, we also propose a duty cycle keeping fine delay line. The proposed DLL is implemented using a 0.13 μm process with a supply voltage of 1.2 V. The active chip area is 0.02 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The operating frequency range of the proposed DLL is from 400 MHz to 800 MHz. At all operating frequencies, the proposed DLL achieves an output duty-cycle error between -0.8% and 1.04% for an input duty cycle from 30% to 70% and the power consumption of the proposed DLL is 3.84 mW.