A Low-Power 16-Channel SiPM Readout Front-end with a Shared SAR ADC in 180 nm CMOS

Abstract

This paper reports a low-power and high-timing resolution silicon photomultiplier (SiPM) readout front-end in a 180 nm CMOS technology. A low-input impedance current buffer employing current feedback is developed to achieve direct charge integration without the use of power-hungry charge-sensitive amplifiers (CSAs). A customized 10-bit SAR ADC is designed for energy digitization. The ADC is shared among 16 readout channels to reduce the chip area and improve power efficiency. The SAR ADC reuses the charge integration capacitor in each readout channel as the ADC sampling capacitor to further lower the power consumption. To reduce the SiPM noise-induced timing measurement error, an on-chip high-pass filter (HPF) based fast pulse generation approach is developed to sharpen the long-tailed SiPM current pulses into fast pulses. With a 1.8 V power supply, the SAR ADC consumes 743 µW at 16 MS/s, and achieves a SNDR of 56.48 dB and a SFDR of 62.53 dB. The on-chip fast pulse generation brings a 35 ps improvement in timing resolution without increasing the number of I/O pin counts. Including the front-end current buffer, current mirrors, charge integrator and the shared ADC, each channel of the readout system consumes 3.8 mW of power with a conversion period of 1 µs.