A low-offset dynamic comparator using bulk biasing technique in digital 65nm CMOS technology

Abstract

This paper presents a low-offset, low-power, high-speed comparator using bulk biasing calibration technique. The adjustment of bulk voltage is realized by analog integration in a feedback loop. The technique can calibrate the offset voltage to small value without reducing speed. The comparator is designed in a standard digital 65nm CMOS technology with 1V supply voltage. The comparator works at 1GHz clock frequency. Simulation results show that it achieves 1.2 mV offset voltage and 1.1mV input referred RMS noise, while dissipating 14fJ/comparison.