A Low-Noise VCO and a Low-Power Frequency Divider in 40-nm CMOS

Abstract

This paper presents a low phase noise voltage-con-trolled oscillator (VCO) with an integrated divide-by-4 current mode logic divider in a 40-nm CMOS process. The VCO is tuned by a 3-bit binary-weighted switched capacitor bank to extend the tuning range. The frequency divider is realized by two cascaded current-mode logic divide-by-2 circuits. An amplifier with neutralizing capacitors to enhance stability is designed as a VCO buffer, which can be used to output the VCO signal or provide an external clock signal to the frequency divider. The VCO achieves a phase noise of −108 dBc/Hz at 1 MHz frequency offset with a 16.0-20.0 GHz tuning range and consumes 4.5 mW at 1.0 V supply. The divide-by-4 circuit operates from 9.3 to 28.3 GHz with 0 dBm input signal and consumes dc power of 5.07 mW.