A Low-Noise High Input Impedance Analog Front-End Design for Neural Recording Implant

Abstract

This paper presents a high input impedance, low-noise, and power-efficient analog front-end (AFE) for neural recording implant. A low-noise, low-power input buffer is used as the input block of the AFE to achieve a high input impedance (over $700 \mathrm{G}\Omega$ @ 0.6 Hz). The buffer is followed by a capacitively-coupled instrumentation amplifier (CCIA) in the second stage to improve the Common-Mode Rejection Ratio (CMRR) and the input-referred noise of the design. A new chopper stabilization control technique is proposed and used in the CCIA stage to reduce the charge injection and clock feedthrough and consequently the high-frequency ripple of the AFE output signal. A programmable gain amplifier (PGA) is designed as the third stage to adjust the overall gain of the AFE. Benefiting from PGA, the AFE is able to adapt its gain with both action potential and local field potential signals. The proposed AFE is designed and simulated using standard TSMC 180nm CMOS process and operates in a wide frequency band of 0.6 Hz to 1000 Hz with low input-referred noise of $2.4 \mu\text{Vrms}$ and a CMRR over 100 dB at 0.6 Hz. The total power consumption is lower than $5.5 \mu \mathrm{W}$ per channel. By applying the proposed chopper stabilization control technique, the amplitude of high-frequency output ripple is reduced by 45% compared to the conventional switched control.