A Low-Leakage Single-Ended 6T SRAM Cell

Abstract

A new six transistor (6T) SRAM cell is presented in this paper for low leakage design. In the proposed SRAM cell, dual threshold voltage and dual power supply techniques are used in order to reduce leakage power dissipation. The new cell operates at 0.6 V in standby mode and at 1V during read operation. The proposed cell has been compared to the conventional 6T-SRAM, using the 65 nm technology. Experimental results show leakage power consumption is reduced by up to 72.7%.