A Low-Cost Improved Method of Raw Bit Error Rate Estimation for NAND Flash Memory of High Storage Density

Kainan Ma,Ming Liu,Hongda Chen,Tao Li,Yibo Yin

doi:10.3390/electronics9111900

Abstract

Cells wear fast in NAND flash memory of high storage density (HSD), so it is very necessary to have a long-term frequent in-time monitoring on its raw bit error rate (RBER) changes through a fast RBER estimation method. As the flash of HSD already has relatively lower reading speed, the method should not further degrade its read performance. This paper proposes an improved estimation method utilizing known data comparison, includes interleaving to balance the uneven error distribution in the flash of HSD, a fast RBER estimation module to make the estimated RBER highly linearly correlated with the actual RBER, and enhancement strategies to accelerate the decoding convergence of low-density parity-check (LDPC) codes and thereby make up the rate penalty caused by the known data. Experimental results show that when RBER is close to the upper bound of LDPC code, the reading efficiency can be increased by 35.8% compared to the case of no rate penalty. The proposed method only occupies 0.039mm2 at 40nm process condition. Hence, the fast, read-performance-improving, and low-cost method is of great application potential on RBER monitoring in the flash of HSD.

Highlights

NAND flash memory technology has been flourishing since the first flash memory being invented by Dr Fujio Masuoka [1] in 1984
The density of storage has been rising from 2D-256Kb single-level cell (SLC) [6], 2D multi-level cell (MLC) [7], and 3D MLC [8], to the current 3D-768Gb triple-level cell (TLC) [3], 3D quad-level cell (QLC) [9,10], and the under-developed penta-level cell (PLC)
Since both types of modulation are possibly used in high storage density (HSD) flash, it is important that the raw bit error rate (RBER) estimation method can be compatible with them both to balance the errors

Summary

Introduction

NAND flash memory technology has been flourishing since the first flash memory being invented by Dr Fujio Masuoka [1] in 1984. As RBER grows fast in HSD NAND flash, it is very necessary to frequently monitor the RBER in a long term so that the error control methods can be executed at the right time to maintain the performance of the flash. The extra redundancy caused by test data reduces the efficiency of reading, especially for the HSD flash which has relatively lower speed but needs the long-term, frequent and in-time RBER monitoring. We proposed an improved and easy-to-implement fast RBER estimation method for HSD NAND flash utilizing true-value data comparison, which can strengthen error performance of error control code (ECC), thereby increasing reading efficiency of the flash.

Data Modulation in NAND Flash

RBER Estimation

Enhancement Strategy for Decoding

Hardware Implementation

Findings

Conclusions