Abstract
To bridge the widening gap between computation requirements of terascale application and communication efficiency faced by gigascale multi-processor system-on-chip devices, a new on-chip communication system, dubbed Wireless Network-on-Chip (WNoC), has been proposed. This work centers on the design of a high-efficient, low-cost, deadlock-free routing scheme for domain-specific irregular mesh WNoCs. A distributed minimal table based routing scheme is designed to facilitate segmented XY-routing. Deadlock-free data transmission is achieved by implementing a new turn classes based buffer ordering scheme. The simulation study demonstrates high routing efficiency, low cost and scalability of the routing scheme and the promising network performance of WNoC.
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