A low-cost 110 dB CMOS IF/limiter amplifier with offset cancellation

Abstract

In this paper we present the design and implementation procedures of a CMOS integrated intermediate frequency (IF) limiting amplifier, which is characterized by its high sensitivity (10 /spl mu/V), high gain (110 dB at 10.7 MHz), low cost, and low output offset voltage (/spl sim/2 /spl mu/V). The amplifier is designed for high sensitivity hearing aids, but can be also utilized in various mobile FM/FSK transceivers. The IF/limiting amplifier consist of 8 direct-coupled differential stages and a limiter stage. A negative feedback network with smart mixing circuit is provided for gain control and automatic offset cancellation. Direct coupling of intermediate stages eliminated the need to integrate so many coupling capacitors, which consume large die area. The amplifier is integrated using 0.8 /spl mu/m standard CMOS technology and occupies a die area of 0.2 mm/sup 2/. The IF/limiter amplifier limits its output to 10 mV at 50 /spl Omega/ load, while consuming no more than 22 mW from a 3.3 V supply.