Abstract
An analog adaptive equalizer based on a feed-forward architecture is implemented in 0.18-mum digital CMOS process. The equalizer is implemented with only digital core devices and operates at 125 Mbps over unshielded-twisted-pair category-5 cable of up to 100 m. Novel low-power circuit and system techniques resulted in 3.7-mW total power consumption and supply voltage operation as low as 1.6 V. The maximum peak-to-peak jitter at the output of the equalizer (including the transmit path driver) under all cable length is 0.33 UI. The total area of the equalizer is 27738 mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .
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