Abstract
A novel device structure that is suitable for practical implementation of lateral superjunction FINFET (SJ-FINFET) on a silicon-on-insulator platform is proposed for sub-200-V rating power applications. The SJ-FINFET structure with heavily doped alternating U-shaped n/p pillars is introduced to minimize both channel and drift resistances and to mitigate electron current crowding near the top of n-drift region. The proposed device structure exhibits low <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,</sub> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sp</sub> with voltage ratings below 200 V. The optimal device characteristics were validated by a 3-D numerical device simulator, ISE-DESSIS. The simulations with trench depths of 2 and 3 mum were analyzed for several different drift lengths and found to be able to overcome the Si limit with the breakdown voltages of 165 and 90 V, respectively.
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