A Low-Voltage 1 Mb FRAM in 0.13 $\mu$m CMOS Featuring Time-to-Digital Sensing for Expanded Operating Margin

Abstract

In the effort to achieve low access energy non-volatile memory, challenges are encountered in sensing data at low power supply voltage. This work presents the design of a ferroelectric random access memory (FRAM) as a promising candidate for this need. The challenges of sensing diminishingly small charge and developing circuits compatible with the scaling of FRAM technology to low voltage and more advanced CMOS nodes are addressed with a time-to-digital sensing scheme. In this work, the 1T1C bitcell signal is analyzed, the circuits for a TDC-based sensing network are presented, and the implementation and operation details of a 1 Mb chip are described. The 1 Mb 1T1C FRAM fabricated in 130 nm CMOS operates from 1.5 V to 1.0 V with corresponding access energy from 19.2 pJ to 9.8 pJ per bit. This approach is generalized to a variety of non-volatile memory technologies.