A low void ratio and low stress potting technology for the multilayer 3D chip on board packaging

Abstract

3D chip on board (CoB) packaging is a promising technique for the 3D IC integration. However, it is facing some difficulties such as voids and high internal stress in the potting process. In this paper, a low void ratio and low stress potting technology for the multilayer 3D CoB packaging is presented. The low void ratio and low stress were obtained through the methods of selecting an appropriate potting compound, optimizing the 3D assembly structure, pretreating the components and potting compound, adjusting the potting and curing conditions. In order to verify the effect of the proposed potting technology, 3D CoB packaged memory modules were fabricated, potted and tested. The result of the finite element analysis showed that, by optimizing the design of the 3D assembly structure, the internal stress of the potted module could be reduced by more than 20%. Progressive profile grinding was used to evaluate the void ratio inside the test samples, the result showed that the average void ratio was less than 1%. Temperature shock test, aging test, mechanical shock and vibration test were also carried out. In these tests, no test samples failed and no defects such as delamination and fracture were observed. This indicated that the potting method proposed in this paper could ensure the reliability of the multilayer 3D CoB packaging.