A low-power ROM using single charge-sharing capacitor and hierarchical bit line

Abstract

This paper describes a low-power read-only memory (ROM) using a single charge-sharing capacitor (SCSC) and hierarchical bit line (HBL). The SCSC-ROM reduces the power consumption in bit lines. It lowers the swing voltage of bit lines to a minimal voltage by using a charge-sharing technique with a single capacitor. It implements the capacitor with dummy bit lines to improve noise immunity and to make it easier to design. Furthermore, the HBL saves power by reducing the capacitance and leakage current in bit lines. The SCSC-ROM also reduces the power consumption in control unit and predecoder by using the hierarchical word line decoder. The simulation result shows that the SCSC-ROM with 4 K/spl times/32 bits consumes only 37% power of a conventional ROM. An SCSC-ROM chip is fabricated in a 0.25-/spl mu/m CMOS process. It consumes 8.2 mW at 240 MHz with 2.5 V.