A Low Power Reconfigurable Analog Baseband Block for Software Defined Radio

Abstract

In this paper, an inverter based transconductor using double CMOS pair is proposed for implementation of a reconfigurable analog baseband block consisting of a variable gain amplifier (VGA) and a second order lowpass Gm-C filter. The centre frequency of the filter is varied using current steering DAC. Major contributions of this paper are: proposal for operating the transconductance (Gm) stage and current steering DAC in sub-threshold region in order to minimize the power dissipation, design of variable gain amplifier (VGA) using switched Gm cells with dummy stages, proposal for a digital tuning technique for the filter based on phase comparison method for compensation against process, voltage and temperature variations. The proposed analog baseband block is designed and implemented on TSMC-0.18?μm CMOS process with 1.8 V supply using gm/Id design methodology. The post layout simulation results demonstrate the tunability of the centre frequency from 100 KHz to 20 MHz which meets the requirements of zero IF receivers for SDR applications. The third order input intercept point (IIP3) is found to be 15 dBVp for an input signal of 100 mVp. The power dissipated by the baseband block is 1 mW and 5 mW at 100 KHz and 20 MHz respectively and it requires silicon area of 0.173 mm2. The SFDR over the entire bandwidth is 58 dB. The proposed approach guarantees the upper bound on THD to be-40 dB for 300 mVpp signal swing. The use of inverters with double CMOS pair results in 34 dB higher PSRR compared to those using push pull inverter.