A low power passive-active ΔΣ modulator with high-resolution employing an integrator with open-loop unity-gain buffer

Abstract

This paper presents a new passive-active ΔΣ modulator with high-resolution and low-power applications. An open-loop unity gain buffer is used to improve the performance of a passive switch capacitor integrator. Since this technique compensates phase and gain errors, there is no need for large capacitors, which result in a great reduction in the chip footprint. The first filter is passive, so the output swing of the amplifier is small but large enough to guarantee the linearity and a relaxed slew rate in the modulator structure, which leads to the low power. Using the second-order modulator with an adequate oversampling ratio leads to the desired SNR. The post-layout simulation of the second-order passive-active modulator is performed in Spectre/Cadence electrical simulator using TSMC 0.18 CMOS model in the standard 0.18 μm CMOS process. The dynamic range of 92.4 dB, peak signal to noise ratio of 88.6 dB, peak signal to noise plus distortions of 82.7 dB were achieved while consuming 1.93 μw in a 500 Hz signal bandwidth at 1.5 V supply, giving a FoMWalden of 0.173 pJ/ conv-step and the FoMSchreier is 176.53 dB.