A Low-Power Logarithmic CMOS Digital-to-Analog Converter for Neural Signal Recording

Abstract

Benefitting from the exponential I-V characteristic curve of CMOS transistors operating in the subthreshold regime, we propose a logarithmic digital-to-analog converter (DAC) for neural recording systems. The reported 8-bit logarithmic DAC converts small voltages with lower resolution and as the input signal increases the resolution of the conversion also increases. The step size changes from 65 mV for the first step to 0.15 mV for the last step. The DAC is designed and implemented in a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology. Operating at 5 MHz the circuit consumes 3.11 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula> from a 1.8-V supply. The input-output characteristic of the DAC resembles a logarithmic curve with the difference between measurement results and the ideal logarithm function having a root-mean-square error (RMSE) of 2.4 mV.