A Low Power High-Speed 12-Bit SAR ADC using Split Capacitor Based DAC at 45 nm CMOS Technology

Abstract

High-performance Integrated Analog-to-Digital Converters (ADCs) are considered an essential part of Digital Signal Processing (DSP) and Microcontroller which connect both analog and digital systems. Furthermore, combining the Successive Approximation Register (SAR) with ADC has attained additional attention in terms of its digital responsiveness and power efficiency. As a result, DSP and Microcontrollers are used globally in electronic products such as biometric sensors and medical equipment. This paper presents a 12-Bit Analog to Digital Converter (ADC) and its encoder is designed with 2 Transistor MUX and 10 Transistor Full adders (12B-2TM-10TFA). The presented design is executed in Cadence Virtuoso 45 nm CMOS (Complementary Metal Oxide Semiconductor) technology. Furthermore, WL (Width/Length) ratio is considered as 2 for designing the full adder. For N-Channel Metal Oxide Semiconductor (NMOS), the width is considered as 120 nm, while for Positive-Channel Metal Oxide Semiconductor (PMOS) is considered as 240 nm, so it can produce better results while designing the proposed 10-T Full Adder. The performance measurements of proposed designs are calculated through power, area, current, and delay and the simulation results displayed that the proposed 12B-2TM-10TFA architecture reduced 39.59% of power, 9.8 % of the area, 18.42% of delay, and 33.39 % of current when compared to the existing folding flash ADC.