A Low Power, High Speed 1.2 V Dynamic Comparator for Analog-to-Digital Converters

Abstract

Abstract The ever-growing demand for high speed, power-efficient and low voltage circuits used in analog to digital converters (ADCs) is driving advancements aimed at increasing power efficiency and speed of dynamic regenerative comparators. This paper proposes a power-efficient, high speed, and low voltage dynamic comparator. The comparator consisting of two operational phases aids in reduction of the mismatch effect of the circuit, thus resulting in a reduced offset voltage. Exhaustive statistical analysis is carried out to determine the delay and offset voltage of the comparator. Thorough and punctilious Monte-Carlo simulation is carried out for the calculation and verification of the designed comparator at various process corners. There is a significant reduction in delay and power consumption of the comparator operating at 3.07 GHz while consuming 0.3 µW. The standard deviation of the offset is found to be 19.01 mV at 1.2 V supply voltage.