A low power, high fill factor and high speed vision pixel in a multitask digital vision chip

Abstract

In this paper a new pixel architecture for use in a multitask digital vision chip is presented. A dynamic comparator because of its low power consumption is used as a single-bit ADC to convert the photodiode signal to the binary data. The processing circuit is based on SIMD parallel processing, and it is configurable to perform different binary image processing operations in high speed with low power consumption. The proposed pixel structure can output the result in each period of its operating frequency, which makes it very suitable for high speed real time applications. The layout of the pixel shows the fill factor of about 27.5 % in a standard 0.18 μm CMOS technology. The post layout simulation results show the pixel consumes 0.254 uW at speed of 250 Kfps.