Abstract
In this paper, we present a hardware friendly binary decision tree (DT) classifier for gas identification. The DT classifier is based on an axis-parallel decision tree implemented as threshold networks—one layer of threshold logic units (TLUs) followed by a programmable binary tree implemented using combinational logic circuits. The proposed DT classifier circuit removes the need for multiplication operation enabling up to 80% savings in terms of silicon area and power compared to oblique based-DT while achieving 91.36% classification accuracy without throughput degradation. The circuit was designed in 0.18 μm Charter CMOS process and tested using a data set acquired with in-house fabricated tin-oxide gas sensors.
Highlights
The last decade has witnessed an increasing interest in gas identification based on gas sensor arrays and pattern analysis for machine olfaction applications [1]
This paper presents a compact single-chip decision tree (DT) classifier based on an axis-parallel DT architecture, which completely removes the need for multiplication operations
Voltages across the sensors are measured and stored in the data acquisition board. This data was used to evaluate the performance of the proposed VLSI friendly DT classifier
Summary
The last decade has witnessed an increasing interest in gas identification based on gas sensor arrays and pattern analysis for machine olfaction applications [1]. Conventional gas identification processing would typically involve signal pre-processing, feature extraction (dimensionality reduction) and classification [1]. 2011, 1 geared towards low cost compact hardware implementation because of the relative complexity involved in feature extraction methods such as principal component analysis (PCA) and linear discriminate analysis (LDA) and pattern recognition algorithms such as artificial neural networks (ANN), K nearest neighbor (KNN) and support vector machines (SVM) [2]. A decision tree (DT) [3] based classifier offers a number of advantages such as smaller number of coefficients for storage and linear computation, making it a viable candidate for on-chip integration.
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