A low power front-end architecture for SiPM readout with integrated ADC and multiplexed readout

Abstract

Silicon Photo-Multiplier (SiPM) detectors are becoming widely used for optical photon and, in conjunction with suited scintillators, for gamma detection in both medical imaging and particle physics experiments. The spatial resolution can be improved by using smaller SiPMs with a corresponding increase in front-end channels density. The timing resolution of the whole system is a function of the detector parameters and of the characteristics of the front-end electronics.We present a low power front-end readout architecture which allows reading out several SiPMs though a single line in order to maximize the number of SiPMs. The design offers good timing performance and includes a simple charge digitizer in every channel.Four different single-ended channel designs have been designed, submitted for fabrication and characterized electronically and with SiPMs. The timing performance is obtained by using a low input impedance, precise threshold setting of a leading edge discriminator and a programmable input dc potential to set the SiPM HV bias on a channel per channel basis. Programmable low- and high-pass filters should allow reducing baseline fluctuations and noise. A simple ADC is implemented by first integrating the signal current and then discharging it at a constant rate until the baseline is reached again. The current consumption of the single channel is typically less than 10 mA. The time and energy information are sent out on a single wire. In order to keep as low as possible the output cabling the signals from different channels can be multiplexed on the same cable. The processing of these signals (extraction of time, ADC amplitude determination and channel number decoding) is performed by an external FPGA.The overall architecture, the front-end designs, and measurements with SiPMs are presented.