A low power error detection in the Chien Search Block for Reed-Solomon code

Abstract

The Reed-Solomon (RS) codes are widely used in communication systems and data storages to recover data from possible errors that occur during transmission and from disk error respectively. This paper describes a new method for error detection in the Chien Search block of RS decoders. The main feature of this method is to introduce a factorization of the error locator polynomial, which allowed us to reduce the number of components required to implement the algorithm of Chien Search Block of RS decoders on FPGA board and consequently reduces the power consumption with a percentage which can reach 50 % compared to the basic RS decoder. The design for Chien Search Block was created and the hardware description language source code was generated and simulated using Quartus software tools.