A Low-Power Bidirectional Link With a Direct Data-Sequencing Blind Oversampling CDR

Abstract

A bidirectional link geared toward mobile I/O applications is presented that leverages the technological advantages of CMOS scaling to improve energy efficiency. Active power consumption is minimized by operating the link at low power-supply voltage (VDD), using a digital intensive design that avoids the use of bias voltage or current DACs, a low swing transmitter with a source-series terminated (SST) driver, and circuit and system co-design. To enable fast transitions between different active and standby power modes, a feedforward clock-and-data recovery (CDR) topology based on blind-oversampling is employed. A direct data-sequencing technique for blind oversampling is proposed that significantly reduces the area and power consumption of conventional techniques, while improving the low-frequency jitter tolerance as well. A prototype serial link comprising of the transmitter, receiver, and an all-digital phase-locked loop (ADPLL) achieves a data-rate of 1.2–5 Gb/s with total energy/bit of 1–1.31 pJ/b. The transceiver (TX and RX) itself has an energy/bit of 0.6 pJ/b. The link occupies an area of 0.041 mm2 in 22-nm CMOS technology and operates at VDD of 0.55–0.7 V.