Abstract
Multi-carrier code division multiple access (MC-CDMA) has a lot of potential in future generations of mobile communications and hence power consumption is important. This paper proposes a pipelined low power architecture for a 64 sub-carrier MC-CDMA receiver. The receiver comprises of two blocks namely the FFT for demodulation of the OFDM signals and a Combiner for de-spreading and equalization. The 64-point FFT block is based on a low power pipelined radix-4 architecture in which order based processing is applied to its second stage to further bring down Its power consumption. The power saving also occurs in the Combiner by disabling the unused blocks through clock gating and also by using a summer and a complementor rather than an adder/subtractor module.
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