A low power and standard-compliant RDO motion estimation hardware architecture for VBSME

Abstract

Motion Estimation (ME) is the most computationally intensive part in the whole video compression process. The ME algorithms can be divided into full search ME (FS) and fast ME (FME). The FS is not suitable for high definition (HD) frame size videos because its relevant high computation load and hard to deal with complex motions in limited search range. A lot of FME algorithms have been proposed which can significantly reduce the computation load compared to FS. Though many kinds of hardware implementations of ME have been proposed, almost all of them fail to consider about the motion vector field (MVF) coherence and rate-distortion (RD) cost which have significant impact to the coding efficiency. In this paper, we propose a novel hardware-oriented motion estimation algorithm called RD Optimized single-MVP-biased FS (RDOMFS), and corresponding highly data reusable hardware architecture. Simulation results show that the proposed ME algorithm performs better RD performance than conventional FME algorithm. The design is implemented with TSMC 0.13 um CMOS technology and costs 103 k gates. At a clock frequency of 61 MHz, the architecture achieves real-time 1920 × 1080 RDO-VBSME at 30 fps.