A Low Power and Low Signal 5-bit 25 MS/s Pipelined ADC for Monolithic Active Pixel Sensors

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> For CMOS monolithic active pixels sensor readout, we developed a 5 bit low power analog to digital converter using a pipelined architecture. A non-resetting sample and hold stage is included to amplify the signal by a factor of 4. Due to the very low level of the incoming signal, this first stage compensates both the amplifier offset effect and the input common mode voltage dispersion. The converter consists of three 1.5 bit sub-ADC and a 2 bit flash. We present the results of a prototype, made of eight ADC channels. The maximum sampling rate is 25 MS/s. The total DC power consumption is 1.7 mW/channel on a 3.3 V supply voltage recommended for the process. But at a reduced 2.5 V supply, it consumes only 1.3 mW. The size of each ADC channel layout is only <formula formulatype="inline"><tex>$43\ \mu{\rm m}\ast 1.43\ {\rm mm}$</tex></formula>. This corresponds to the pitch of two pixel columns each one would be 20 <formula formulatype="inline"><tex>$\mu{\rm m}$</tex></formula> wide. The full analog part of the converter can be quickly switched to a standby idle mode in less than 1 <formula formulatype="inline"><tex>$\mu{\rm s}$</tex></formula>; thus reducing the power dissipation to a ratio better than 1/1000. This fast shutdown is very important for the ILC vertex detector as the total DC power dissipation becomes directly proportional to the low beam duty cycle. </para>