A low power and high-speed hardware accelerator for Wireless Body Sensor Network (WBSN)

Abstract

In this work, an efficient hardware accelerator is developed with techniques for processing various parameters of the body in the case of the Wireless Body Sensor Network (WBSN). Accelerators reduce data for storing purposes and increase speed in real time. The proposed design also decreases the number of gate counts after synthesis which in turn decreases the area. Our paper proposes the idea of a high-speed HA as an efficient means to transmit information at high speed. Memory, predictors, encryption, and error-control coding make up the Hardware Assembler. The technique provides data integrity and safety while providing high speed when connected with controllers. Simulation and synthesis operations of the proposed scheme are performed using Vivado Xilinx software. Our experimental analysis shows that the proposed scheme implemented with 28 nm Technology on Zynq SOC produces 11mw of power and utilizes 4.8% of FPGA resources.