A Low Power and Error Tolerant Structure for Motion Estimation Core in H. 264/AVC Standard

Abstract

Motion estimation is widely used for removing temporal data redundancy in many video coding systems. Motion estimation core is one of the biggest and the most complex cores in many of video coding standards. Nowadays, video systems are embedded into many of portable devices; hence, they need have a trade of between their power consumption and quality of output. Hardware failure is the most important reason of quality degradation in the RT level. In this paper, two RT level low power error tolerant methods are proposed for this important video compression core. The proposed methods can be used in conjunction with other higher or lower level error tolerant and power reduction methods that have been previously proposed for this component. Experimental results show that our methods have smaller area overhead, higher reliability, and lower power consumption than the existing methods for motion estimation. General Terms VLSI system design, Fault tolerant systems, Video coding cores.