A Low-Power 100 MHz Analog FIR Filter for PRML Equalization

Abstract

This paper presents design of a low-power 100 MHz analog FIR filter for PRML equalization used in the read channel of hard disk drives. The chip consists of 16 channels to provide 15-tap FIR filter operation. By using rotating clocks for sample/hold operation with one dummy channel, timing constraints can be relieved, which results in low-power consumption. The chip incorporates the parallel array of sample-and-hold amplifiers for analog delay line. The sample-and-hold amplifier includes the open-loop unity-gain amplifier with gain-control circuit using replica-biasing scheme, which also improves uniformity among amplifiers. It was fabricated in a 0.8-mm CMOS technology and consumes power of 200 mW for \pm 1.65 V power supply voltage.