A Low Oversampling Ratio 11-bit, 10.6-MHz Switched-Capacitor Delta-Sigma Modulator for Wideband Applications

Abstract

This paper presents the design and implementation of a sixth-order delta-sigma modulator (DSM) for wide-band applications. The 6th-order MASH DSM uses a 2-2-2-cascade topology with optimized noise transfer function (NTF). It is implemented using switched-capacitor circuits with a sampling rate of 64-MHz. For a low oversampling ratio of 6, the DSM can achieve a peak signal-to-noise-and-distortion ratio (SNDR) of 67.9-dB and a DR of 68-dB. The 6th-order MASH (multi-stage noise shaping) wideband delta-sigma modulator (WDSM) features optimum NTF and uses 3-level quantizers to achieve high dynamic range performance. For a clock frequency of 64-MHz, the WDSM dissipates a power of 25.4-mW from a 1.8-V supply. The active area is less than 1-mm2 in a 0.18-mum single-poly, six-metal CMOS technology.