A low overhead fault tolerant routing scheme for 3D Networks-on-Chip

Abstract

Three-dimensional integrated circuits (3D-ICs) offer a significant opportunity to e nhance the performance of emerging chip multiprocessors (CMPs) using high density stacked device integration and shorter through silicon via (TSV) interconnects that can alleviate some of the problems associated with interconnect scaling in s ub-65nm CMOS technologies. However, network-on-chip (NoC) fabrics that will connect the cores together in 3D-ICs will increasingly be susceptible to permanent and intermittent faults, which can cause catastrophic system failure. To overcome these faults, NoC routing schemes can be enhanced by adding fault tolerance capabilities, so that they can adapt communication flows to follow fault-free paths. Existing work has proposed various fault tolerant routing algorithms for 2D NoCs. In this paper, for the first time, we investigate fault tolerant routing schemes in 3D NoCs. To achieve high arrival rates in the presence of faults, we propose a novel low-overhead fault tolerant routing scheme (4NP-First) for 3D NoCs. The proposed scheme is shown to have better resilience and adaptivity to f aults compared to e xisting dimension-order, turn-model, and stochastic random walk based 2D NoC routing schemes extended to 3D NoCs.