A low offset chopper amplifier with three-stage nested Miller configuration

Abstract

A low offset, low noise chopper amplifier for sensor system application is presented. Low 1/f noise is achieved by employing chopper technique, and low offset is achieved by employing residual offset suppression circuit. The open-loop gain is extended using three-stage nested Miller configuration. The chip was implemented in 0.5 μm 2P3M CMOS process. The amplifier is featured by an open-loop gain of 135 dB and a GBW of 3 MHz. The measured offset voltage is 3 μV, and the equivalent input noise power spectrum density at 1 Hz is 96 nV / \(\sqrt {Hz} \).