A Low-Noise High-Frame-Rate 1-D Decoding Readout Architecture for Stacked Image Sensors

Abstract

The continuously increasing array resolution of CMOS imagers poses a great challenge in combining high-frame-rate and low light detection in the same sensor. To cope with this, parallel readout architectures are needed. This paper proposes a readout architecture for 8K stacked image sensors, which uses a novel 1D decoding readout based on block-of-pixels and incremental-sigma-delta ADCs. The proposed 1D decoding system reduces the control lines of the pixels and allows a simpler decoding, an increased parallelism, and an improved robustness over process yield. The experimental results from a test chip implemented in a standard CIS technology show that at 10 μm pixel pitch, the proposed readout architecture can achieve a high-frame-rate of 730 frames/s and a low read noise of 1.4 e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> . In a real stacked implementation, the frame rate can further increase to about 960 frames/s at 8K resolution, at the cost of a slight increase in thermal noise by 14 μV.