A low leakage pull-down network for PLL with 6.7 dB improvement in reference spur

Abstract

A leakage current reduction technique is proposed for the pull-down network (PDN), which is used to hibernate the Phase-locked loop (PLL). Due to low leakage current, the PDN results in a PLL with lower reference spur. The switch leakage is minimized by biasing the MOSFET with V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> S <; 0. Proposed method reduces the leakage current by at least an order of magnitude. A prototype PLL was built in TSMC 0.18 μm CMOS technology. An improvement of 6.7 dB in reference spur is measured compared to the conventional PLL.