Abstract
A pulsewidth control loop (PWCL) based on a delay-locked loop (DLL) is presented in the paper. The duty cycle of the proposed PWCL can be adjusted from 10% to 90% in 10% step. The circuit is designed and simulated using TSMC 0.13 mum CMOS process. The operation frequency range is from 770 MHz to 1.43 GHz. The locking time of DLL is less than 15 ns within the operation frequency band. The power dissipation is 3 mW at 1.2 V voltage supply. The peak-to-peak jitter is less than 2 ps at an input clock frequency of 1.25 GHz while adjusting various duty cycles.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
