A Low-jitter Charge-pumped PLL for LiDAR Detectors

Abstract

A low-jitter charge-pumped phase-locked loop (CPPLL) with four-stage differential delay units is implemented in 180 nm standard CMOS technology. Not only a current-steering technique is adopted to eliminate charge injection and clock feed-through effects, but also a frequency divider with a retiming structure is used to ensure the high accuracy of the system feedback loop. The voltage-controlled oscillator adopts a gated-ring structure to achieve a stable and controllable clock. The prototype of the CPPLL occupies 0.184 , and results reveal that when the reference clock is 50 MHz, the output frequency is locked at 800 MHz accurately. The phase noise is as low as -140 dBc/Hz @1 MHz, with a peak-to-peak jitter of 4.36 ps. Meanwhile, an ultra-low root-mean-square (RMS) jitter of 0.161 ps is obtained. At the output spectrum of 800 MHz, the reference spur is merely -72 dBc. These results highlight the CPPLL's outstanding performance in phase noise, jitter, and stability, making it well-suited for high-precision integrated LiDAR.