Abstract
In this paper, a novel energy reduction technique for High Efficiency Video Coding (HEVC) Inverse Discrete Cosine Transform (IDCT) for all Transform Unit (TU) sizes is proposed. An efficient HEVC 2D IDCT hardware for all TU sizes is also designed and implemented using Verilog HDL. The proposed hardware can decode 48 Quad HD (3840×2160) video frames per second. The proposed technique reduced its energy consumption up to 23%.
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