A low damage Si3N4 sidewall spacer process for self-aligned sub-100 nm III–V MOSFETs

Abstract

This paper investigates a low damage reactive ion etch (RIE) process to make thin silicon nitride sidewall spacers for the fabrication of self-aligned sub-100nm gate length III–V metal–oxide–semiconductor field-effect-transistors (MOSFETs). Self-alignment is essential to minimize the contribution to the parasitic series source/drain resistance (RSD) from the access region between the ohmic contact and the gate, whilst retaining the overall electrostatic integrity of the device. In this work, a blanket Si3N4 was deposited by room temperature inductively coupled plasma chemical vapour deposition (ICP-CVD) and etched by reactive ion etching in a SF6/N2 based chemistry. Conditions were optimised to ensure low damage to the underlying device layer stack. This process has successfully produced thin Si3N4 spacers for fabricating self-aligned GaAs MOSFETs. The sheet resistance of III–V MOSFET materials was monitored as a function of etch parameters to assess the impact of damage related effects on the electronic characteristics of the underlying material. The etching profile and the sheet resistance of the device layer structures were characterised by using scanning electronic microscope (SEM) and sonogage, respectively.