A Low-Cost VLSI Architecture for Fault-Tolerant Fusion Center in Wireless Sensor Networks

Abstract

A fault-tolerant distributed decision fusion in the presence of sensor faults via collaborative sensor fault detection (CSFD) was proposed in our previous research . The scheme can identify the faulty nodes efficiently and improve the performance of the decision fusion significantly. It achieves very good performance at the expense of such extensive computations as exponent and multiplication/division in the detecting process. In many real-time WSN applications, the fusion center might be implemented in an ASIC and included in a standalone device. Therefore, a simple and efficient decision fusion scheme requiring lower hardware cost and power consumption is extremely desired. In this paper, we propose the approximated collaborative sensor fault detection (ACSFD) scheme and its VLSI architecture. Given the low circuit complexity, it is suitable for hardware implementation. The ACSFD circuit contains 9265 gates and requires a core size of 368 × 358 ¿m <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> by using TSMC 0.18 ¿m cell library. It can operate at a clock rate of 102 MHz with a power consumption of 2.516 mW. Simulation results indicate that ACSFD performs better in fault tolerance than the conventional approach.