A low cost jitter estimation and ADC spectral testing method

Abstract

Clock jitter is a crucial factor in high speed and high performance Analog-to-Digital Converter (ADC) testing. Random clock jitter increases the noise floor in the ADC output spectrum making it difficult to obtain the true ADC Signal to Noise Ratio (SNR). Periodic Jitter generates spurs in the ADC output spectrum. Another well-known challenge is to achieve precise coherent sampling. This paper proposes an efficient and accurate ADC spectral testing method that completely eliminates the need for coherent sampling and very effectively separate clock jitter from ADC noise, thus allowing the true ADC spectral parameters to be accurately tested with an imprecise sampling clock. Simulation results of ADCs with different resolutions demonstrate the functionality and accuracy of the method.