A Low-Complexity Embedded Compression Codec Design With Rate Control for High-Definition Video

Abstract

A hardwired design of embedded compression engine targeting the reduction of full high-definition (HD) video transmission bandwidth over the wireless network is developed. It adopts an intra-coding framework and supports both lossless and rate-controlled near lossless compression options. The lossless compression algorithm is based on a simplified Context-Based, Adaptive, Lossless Image Coding (CALIC) scheme featuring pixelwise gradient-adjusted prediction and error-feedback mechanism. To reduce the implementation complexity, an adaptive Golomb-Rice coding scheme in conjunction with a context modeling technique is used in lieu of an adaptive arithmetic coder. With the measures of prediction adjustment, the near lossless compression option can be implemented on top of the lossless compression engine with minimized overhead. An efficient bit-rate control scheme is also developed and can support rate or distortion-constrained controls. For full HD (previously encoded) and nonfull HD test sequences, the lossless compression ratio of the proposed scheme, on average, is 21% and 46%, respectively, better than the Joint Photographic Experts Group-Lossless Standard and the Fast, Efficient Lossless Image Compression System (FELICS) schemes. The near lossless compression option can offer additional 6%–20% bit-rate reduction while keeping the Peak Signal-to-Noise Ratio value 50 dB or higher. The codec is further optimized complexity-wise to facilitate a high-throughput chip implementation. It features a five-stage pipelined architecture and two parallel computing kernels to enhance the throughput. Fabricated using the Taiwan semiconductor manufacturing company 90-nm complementary metal-oxide–semiconductor technology, the design can operate at 200 MHz and supports a 64 frames/s processing rate for full HD videos.