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Abstract
In this paper, a very-large-scale integration (VLSI) design that can support high-efficiency video coding inverse discrete cosine transform (IDCT) for multiple transform sizes is proposed. The proposed two-dimensional (2-D) IDCT is implemented at a low area by using a single one-dimensional (1-D) IDCT core with a transpose memory. The proposed 1-D IDCT core decomposes a 32-point transform into 16-, 8-, and 4-point matrix products according to the symmetric property of the transform coefficient. Moreover, we use the shift-and-add unit to share hardware resources between multiple transform dimension matrix products. The 1-D IDCT core can simultaneously calculate the first- and second-dimensional data. The results indicate that the proposed 2-D IDCT core has a throughput rate of 250 MP/s, with only 110 K gate counts when implemented into the Taiwan semiconductor manufacturing (TSMC) 90-nm complementary metal-oxide-semiconductor (CMOS) technology. The results show the proposed circuit has the smallest area supporting the multiple transform sizes.
Highlights
The video compression technique is utilized in digital image processing to reduce the redundancy of video information and increase the storage capacity and transmission rate efficiently
3 Results and discussion To indicate the performance of the proposed circuit, the very-large-scale integration implementation is described in the following subsection
3.1 Chip implementation The proposed 32-point 2-D inverse discrete cosine transform (IDCT) core is implemented in a 1-V Taiwan semiconductor manufacturing (TSMC) 90-nm 1P9M complementary metal-oxide-semiconductor (CMOS) process
Summary
The video compression technique is utilized in digital image processing to reduce the redundancy of video information and increase the storage capacity and transmission rate efficiently. Many researchers have implemented integer transforms, especially for HEVC [15,16,17,18,19,20,21,22,23,24]. The rowcolumn decomposition structure is widely used to design a two-dimensional (2-D) transform core. The 2D transform core is directly implemented using two onedimensional (1-D) cores and a transposed memory. This method can achieve a high-throughput rate; it results in the wastage of a considerable amount of circuit
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