A Lossy Capacitance Measurement Circuit Based on Analog Lock-in Detection

Abstract

This paper presents a lossy capacitance measuring circuit which is based on analog lock-in detection technique. Lossy capacitance can be modelled as a pure capacitor connected in parallel with a resistor. The measurement circuit mechanism consists of an excitation signal to drive the lossy capacitance, a transimpedance amplifier to produce a voltage, and a lock-in detection circuit to extract lossy values of capacitance. The lock-in detector multiplies its input with a square wave using switches and filters out high frequencies to give a DC output that is actually in proportional to the measured values. A field programmable gate array is employed to generate direct digital synthesis based sinusoidal excitation signal to generate reference signals required for demodulation and to measure the output of lock-in detection. The phase shift between the excitation signal and reference signals is controlled accurately in digital domain. Thus, due to the phase mismatch, errors are properly reduced. Also, analog phase shifter and analog switch-driving circuits are no longer required. Three different lossy capacitors realized using discrete components are simulated and tested. The maximum relative error is 1.62 % for the resistance measurement and 6.38 % for the capacitance measurement.