Abstract
A single-poly floating gate non volatile memory cell is presented. In this device the second poly layer is removed to make the device compatible with standard logic CMOS process. An array of cells with high storage density has been fabricated on a standard 0.25 /spl mu/m CMOS process with a special architecture. All memory cells tolerate 60000 cycles of endurance test and show 10 years of data retention. Using this cell, a small to medium size (typically 64 K*8b) Flash EEPROM array would be integrated in standard logic CMOS process.
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