A Linear-Logarithmic CMOS Image Sensor With Pixel-FPN Reduction and Tunable Response Curve

Abstract

This paper presents a high dynamic range (DR) linear-logarithmic (Lin-Log) CMOS image sensor (CIS) pixel with threshold voltage cancellation technique for pixel fixed pattern noise (PFPN) reduction. A tunable pixel response curve was applied for different environments. To avoid the gain loss of source follower in conventional APS structure, a column shared-amplifier with programmable gain was also applied. A prototype high DR Lin-Log CIS chip consisting of 100 × 100 5-T pixel array with n+/p-sub photodiode, a pixel area of 6 × 6 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and 3.3 V operation was designed and fabricated in TSMC 0.18 μm CMOS 1P6M standard process. The measured results achieved a DR of 143 dB, a PFPN related to sensitivity in logarithmic response (rms/log-sensitivity) of 1.96%, and a PFPN related to full-swing in logarithmic response (rms/Vlog-swing) of 0.45%. Linear and logarithmic sensitivity were 651 mV/lux-s and 55 mV per decade of illumination, respectively, at 50 fps. The temporal noise and power consumption were 0.746 m Vrms and 1.88 mW, respectively.