A linear CMOS balanced output transconductor using double differential pair with source degeneration and adaptive biasing

Abstract

This paper presents two new configurations for linear CMOS balanced output transconductor. The proposed circuits employ three types of linearization techniques which are previously reported in the literature. The three techniques are the source degeneration, double differential pair technique and the adaptive biasing. The second proposed configuration achieves rail to rail operation with low THD in compare with other linearization techniques. Up to 1 MHz, the third-order inter-modulation (IM3) remains below −60 dB for 0.4 V input differential voltage at 1.2 V supply voltage. The linearity performance of proposed OTA circuits are validated by computer simulation using TSMC 90 nm technology.