A LIMITED SHARED OUTPUT BUFFER SWITCH FOR ATM

Abstract

In this paper, a new switch architecture is proposed for the ATM exchange. The architecture is a hybrid version of shared and dedicated output buffer memory switches. Namely, the switch consists of a single shared buffer memory and N first in first out (FIFO) buffers, where N is the switch size. An incoming cell to the i-th output port is stored into the shared buffer memory and the corresponding buffer address is stored into the i-th FIFO buffer, where i = 1, 2, N. The addresses in the i-th FIFO buffer are used to read cells from the shared buffer memory and send them to the i-th output port. Incoming cells are converted to bit parallel data and multiplexed in time, which makes the switch realizable using the current available VLSI technology. Analytical and experimental results show that the proposed switch performs not worse than a shared output buffer switch does. The proposed switch needs far less (resp., a little more) memory than that of a dedicated (resp., shared) output buffer switch for a comparable performance. Nevertheless, the implementation of the proposed switch is simple and the broadcasting is very easy, which may be a main drawback of a shared output buffer switch.