Abstract
Negative bias temperature instability (NBTI) has become one of the major causes for temporal reliability degradation of nanoscale circuits. Due to its complex dependence on operating conditions, it is a tremendous challenge to the existing timing analysis flow. In order to get the accurate aged delay of the circuit, previous research mainly focused on the gate level or lower. This paper proposes a low-runtime and high-accuracy machining learning framework on the circuit path level firstly, which can be formulated as a multi-input–multioutput problem and solved using a linear regression model. A large number of worst-case path candidates from ISCAS’85, ISCAS’89, and ITC’99 benchmarks were used for training and inference in the experiment. The results show that our proposed approach achieves significant runtime speed-up with minimal loss of accuracy.
Highlights
Invasive uninterrupted scaling of CMOS and fin field-effect transistor (FinFET) technologies to nanoscale level leads to various fallouts such as variability of process parameters and aging [1].Fabrication-induced geometric and electrical parameter variations, e.g., changes in device effective channel length and threshold voltage, have introduced large-scale variability of circuit performance.runtime aging effects, such as electromigration, thermal cycling, and negative bias temperature instability (NBTI), have become another serious concern in nanoscale integrated circuit design [2].NBTI is known to be the most critical reliability issue that can affect circuit lifetime [3,4]
From the numerical solution of the standard reaction diffusion (R–D) model, the NBTI degradation models were developed, which formed the basis for higher-level research
Traditional circuit aged delay is mostly based on the look up table (LUT) scheme
Summary
Invasive uninterrupted scaling of CMOS and fin field-effect transistor (FinFET) technologies to nanoscale level leads to various fallouts such as variability of process parameters and aging [1]. Due to NBTI, the threshold voltage (|Vth |) of the transistor increases with time, resulting in a reduction in drive current. On the contrary, when the pMOS is off (Vgs = 0), |Vth | will decrease gradually before stress injection, and pMOS degradation is relaxed. This condition is defined as the recovery phase of NBTI. Electronics 2020, 9, 1976 is to propose a regression-based machine learning algorithm in high level due to NBTI effects, which is the first such paper in the literature to the best of the authors’ knowledge. The rest of the article is organized as follows: Section 2 introduces the related research on NBTI degradation comprehensively from physical to circuit level.
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